Most significant bit operand in part-select of vector wire is illegal
0
I want to make a parameterized FIR filter in verilog on xilinix. This is my code:
module FIRFilter(xInput, clock, reset, filterCoeff, yOutput);
parameter inputBits = 8, lengthOfFilter = 4, coeffBitLength = 8, lengthOfCoeff = lengthOfFilter + 1, outputBitWdth = 2 * inputBits;
input [(coeffBitLength * lengthOfCoeff) - 1 : 0] filterCoeff;
input clock, reset;
input [inputBits - 1 : 0] xInput;
reg [outputBitWdth - 1 : 0] addWires [lengthOfFilter - 1 : 0];
output reg [outputBitWdth - 1 : 0] yOutput;
reg [inputBits - 1 : 0] registers [lengthOfFilter - 1 : 0];
integer i, j;
always @ (posedge clock, posedge reset)
begin
if(reset)
begin
for(i = 0; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= 0;
end
end
else
begin
registers[0] <= xInput;
for(i = 1; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= registers[i - 1];
end
end
end
always @ (posedge clock)
begin
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) - 1 : (lengthOfFilter - 1) * coeffBitLength] * xInput;
for(j = 1; j < lengthOfFilter; j = j + 1)
begin
addWires[j] = (filterCoeff[((j + 1) * coeffBitLength) - 1 : j * coeffBitLength] * registers[j - 1]) + addWires[j - 1];
end
yOutput = (filterCoeff[coeffBitLength - 1 : 0] * registers[lengthOfFilter - 1]) + addWires[lengthOfFilter - 1];
end
endmodule
But I keep getting this error
ERROR:HDLCompilers:109 - "FIRFilter.v" line 33 Most significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:110 - "FIRFilter.v" line 33 Least significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:45 - "FIRFilter.v" line 33 Illegal right hand side of blocking assignment
I searched online for the solution but haven't got any satisfactory answer.
Can someone help me with the this?
verilog
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
add a comment |
0
I want to make a parameterized FIR filter in verilog on xilinix. This is my code:
module FIRFilter(xInput, clock, reset, filterCoeff, yOutput);
parameter inputBits = 8, lengthOfFilter = 4, coeffBitLength = 8, lengthOfCoeff = lengthOfFilter + 1, outputBitWdth = 2 * inputBits;
input [(coeffBitLength * lengthOfCoeff) - 1 : 0] filterCoeff;
input clock, reset;
input [inputBits - 1 : 0] xInput;
reg [outputBitWdth - 1 : 0] addWires [lengthOfFilter - 1 : 0];
output reg [outputBitWdth - 1 : 0] yOutput;
reg [inputBits - 1 : 0] registers [lengthOfFilter - 1 : 0];
integer i, j;
always @ (posedge clock, posedge reset)
begin
if(reset)
begin
for(i = 0; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= 0;
end
end
else
begin
registers[0] <= xInput;
for(i = 1; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= registers[i - 1];
end
end
end
always @ (posedge clock)
begin
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) - 1 : (lengthOfFilter - 1) * coeffBitLength] * xInput;
for(j = 1; j < lengthOfFilter; j = j + 1)
begin
addWires[j] = (filterCoeff[((j + 1) * coeffBitLength) - 1 : j * coeffBitLength] * registers[j - 1]) + addWires[j - 1];
end
yOutput = (filterCoeff[coeffBitLength - 1 : 0] * registers[lengthOfFilter - 1]) + addWires[lengthOfFilter - 1];
end
endmodule
But I keep getting this error
ERROR:HDLCompilers:109 - "FIRFilter.v" line 33 Most significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:110 - "FIRFilter.v" line 33 Least significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:45 - "FIRFilter.v" line 33 Illegal right hand side of blocking assignment
I searched online for the solution but haven't got any satisfactory answer.
Can someone help me with the this?
verilog
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
You should use nonblocking assignments (<=) in your 2ndalwaysblock.
– toolic
Nov 24 '18 at 13:54
You might get more helpful error messages on edaplayground. I getIllegal operand for constant expressionon Incisive.
– toolic
Nov 24 '18 at 13:57
add a comment |
0
0
0
I want to make a parameterized FIR filter in verilog on xilinix. This is my code:
module FIRFilter(xInput, clock, reset, filterCoeff, yOutput);
parameter inputBits = 8, lengthOfFilter = 4, coeffBitLength = 8, lengthOfCoeff = lengthOfFilter + 1, outputBitWdth = 2 * inputBits;
input [(coeffBitLength * lengthOfCoeff) - 1 : 0] filterCoeff;
input clock, reset;
input [inputBits - 1 : 0] xInput;
reg [outputBitWdth - 1 : 0] addWires [lengthOfFilter - 1 : 0];
output reg [outputBitWdth - 1 : 0] yOutput;
reg [inputBits - 1 : 0] registers [lengthOfFilter - 1 : 0];
integer i, j;
always @ (posedge clock, posedge reset)
begin
if(reset)
begin
for(i = 0; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= 0;
end
end
else
begin
registers[0] <= xInput;
for(i = 1; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= registers[i - 1];
end
end
end
always @ (posedge clock)
begin
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) - 1 : (lengthOfFilter - 1) * coeffBitLength] * xInput;
for(j = 1; j < lengthOfFilter; j = j + 1)
begin
addWires[j] = (filterCoeff[((j + 1) * coeffBitLength) - 1 : j * coeffBitLength] * registers[j - 1]) + addWires[j - 1];
end
yOutput = (filterCoeff[coeffBitLength - 1 : 0] * registers[lengthOfFilter - 1]) + addWires[lengthOfFilter - 1];
end
endmodule
But I keep getting this error
ERROR:HDLCompilers:109 - "FIRFilter.v" line 33 Most significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:110 - "FIRFilter.v" line 33 Least significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:45 - "FIRFilter.v" line 33 Illegal right hand side of blocking assignment
I searched online for the solution but haven't got any satisfactory answer.
Can someone help me with the this?
verilog
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
I want to make a parameterized FIR filter in verilog on xilinix. This is my code:
module FIRFilter(xInput, clock, reset, filterCoeff, yOutput);
parameter inputBits = 8, lengthOfFilter = 4, coeffBitLength = 8, lengthOfCoeff = lengthOfFilter + 1, outputBitWdth = 2 * inputBits;
input [(coeffBitLength * lengthOfCoeff) - 1 : 0] filterCoeff;
input clock, reset;
input [inputBits - 1 : 0] xInput;
reg [outputBitWdth - 1 : 0] addWires [lengthOfFilter - 1 : 0];
output reg [outputBitWdth - 1 : 0] yOutput;
reg [inputBits - 1 : 0] registers [lengthOfFilter - 1 : 0];
integer i, j;
always @ (posedge clock, posedge reset)
begin
if(reset)
begin
for(i = 0; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= 0;
end
end
else
begin
registers[0] <= xInput;
for(i = 1; i < lengthOfFilter; i = i + 1)
begin
registers[i] <= registers[i - 1];
end
end
end
always @ (posedge clock)
begin
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) - 1 : (lengthOfFilter - 1) * coeffBitLength] * xInput;
for(j = 1; j < lengthOfFilter; j = j + 1)
begin
addWires[j] = (filterCoeff[((j + 1) * coeffBitLength) - 1 : j * coeffBitLength] * registers[j - 1]) + addWires[j - 1];
end
yOutput = (filterCoeff[coeffBitLength - 1 : 0] * registers[lengthOfFilter - 1]) + addWires[lengthOfFilter - 1];
end
endmodule
But I keep getting this error
ERROR:HDLCompilers:109 - "FIRFilter.v" line 33 Most significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:110 - "FIRFilter.v" line 33 Least significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:45 - "FIRFilter.v" line 33 Illegal right hand side of blocking assignment
I searched online for the solution but haven't got any satisfactory answer.
Can someone help me with the this?
verilog
verilog
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
asked Nov 24 '18 at 11:46
Usman ManiUsman Mani
32
32
You should use nonblocking assignments (<=) in your 2ndalwaysblock.
– toolic
Nov 24 '18 at 13:54
You might get more helpful error messages on edaplayground. I getIllegal operand for constant expressionon Incisive.
– toolic
Nov 24 '18 at 13:57
add a comment |
You should use nonblocking assignments (<=) in your 2ndalwaysblock.
– toolic
Nov 24 '18 at 13:54
You might get more helpful error messages on edaplayground. I getIllegal operand for constant expressionon Incisive.
– toolic
Nov 24 '18 at 13:57
You should use nonblocking assignments (
<=) in your 2nd always block.– toolic
Nov 24 '18 at 13:54
You should use nonblocking assignments (
<=) in your 2nd always block.– toolic
Nov 24 '18 at 13:54
You might get more helpful error messages on edaplayground. I get
Illegal operand for constant expression on Incisive.– toolic
Nov 24 '18 at 13:57
You might get more helpful error messages on edaplayground. I get
Illegal operand for constant expression on Incisive.– toolic
Nov 24 '18 at 13:57
add a comment |
1 Answer
1
active
oldest
votes
0
Verilog does not allow part selects signal[msb:lsb] where msb and lsb are not constants. You can use another construct called an indexed part select where you specify a constant width, but a variable offset signal[offset+:width]
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) +:coeffBitLength] * xInput;
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
Cheers mate. That helped
– Usman Mani
Nov 25 '18 at 15:16
add a comment |
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1 Answer
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0
Verilog does not allow part selects signal[msb:lsb] where msb and lsb are not constants. You can use another construct called an indexed part select where you specify a constant width, but a variable offset signal[offset+:width]
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) +:coeffBitLength] * xInput;
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
Cheers mate. That helped
– Usman Mani
Nov 25 '18 at 15:16
add a comment |
0
Verilog does not allow part selects signal[msb:lsb] where msb and lsb are not constants. You can use another construct called an indexed part select where you specify a constant width, but a variable offset signal[offset+:width]
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) +:coeffBitLength] * xInput;
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
Cheers mate. That helped
– Usman Mani
Nov 25 '18 at 15:16
add a comment |
0
0
0
Verilog does not allow part selects signal[msb:lsb] where msb and lsb are not constants. You can use another construct called an indexed part select where you specify a constant width, but a variable offset signal[offset+:width]
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) +:coeffBitLength] * xInput;
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
Verilog does not allow part selects signal[msb:lsb] where msb and lsb are not constants. You can use another construct called an indexed part select where you specify a constant width, but a variable offset signal[offset+:width]
addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) +:coeffBitLength] * xInput;
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
answered Nov 24 '18 at 15:07
dave_59dave_59
20.4k21537
20.4k21537
Cheers mate. That helped
– Usman Mani
Nov 25 '18 at 15:16
add a comment |
Cheers mate. That helped
– Usman Mani
Nov 25 '18 at 15:16
Cheers mate. That helped
– Usman Mani
Nov 25 '18 at 15:16
Cheers mate. That helped
– Usman Mani
Nov 25 '18 at 15:16
add a comment |
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You should use nonblocking assignments (
<=) in your 2ndalwaysblock.– toolic
Nov 24 '18 at 13:54
You might get more helpful error messages on edaplayground. I get
Illegal operand for constant expressionon Incisive.– toolic
Nov 24 '18 at 13:57