Ytukyg

The introduction to computer system book shows a difference between CISC & RISC as the following.

CISC: Implementation artifacts hidden from machinelevel
programs. The ISA provides a clean abstraction
between programs and how they get executed.

RISC:Implementation artifacts exposed to machine-level
programs. Some RISC machines prohibit particular
instruction sequences and have jumps that do
not take effect until the following instruction is executed.
The compiler is given the task of optimizing
performance within these constraints.

And im wondering what "particular instruction sequences" is prohibited, and why?

What the author is trying to convey is that CISC ISAs are better at hiding micro-architecture details from the programmer than RISC. A CISC ISA exposes instructions that denote a specific operation that is not necessarily tied to the way a micro-architecture implementation might execute that operation.

Let's say we want want to move data from memory position A to another B -- A CISC architecture would expose that operation as an instruction similar to this: "mov B, A" (macro-op). Now, one way one can implement this at the micro-architecture level is to do it in two steps, i.e. execute two instructions (micro-ops) -- Load data from A to a register and then store from that register into memory position B. Another way to do this is to offload the moving of data to a co-processor that might be more efficient at moving the data around in memory (DMA engine). Either way, the programmer encodes the operation as a single instruction (the "mov" instruction) without requiring knowledge of how the operation will actually be executed at the micro-architecture level

On the other hand, RISC ISAs tend to (although not always) expose operations as they actually execute in the processor (i.e. in the form of micro-ops) and it's the job of the programmer to compose those operation into more complex ones that do what the programmer wants the program to do. The move operation described above as an example would have to be explicitly encoded as two instructions or using DMA.

The example the author gives as RISC ISAs exposing implementation details ("artifacts"), is about branch delay slots where the instruction following a branch will always be executed independently if the branch is taken or not. This is due to the pipelining of instructions which is a micro-architecture technique used to speed up execution. In this case, the ISA is exposing a micro-architecture detail that the programmer needs to be aware of to guarantee program correctness. Pipelining instructions can also create other pipeline hazzards which is what I think the author means as "prohibited instruction sequences". These instruction sequences are no prohibited per se, you can execute them but they will produce incorrect results.

Hope this helps.