Ytukyg

I’ve designed lot of ‘simple’ PCBs for hobby and proof-of-concept purposes, but never for (mass)manufacturing. In order to do so in the future, and further expanding my design skills and knowledge, I’m exploring the different package outline standards.

By now I learned there is no such thing as “one main standard for all packages”. Instead, there are multiple standards for multiple packages, set up by multiple organizations. ‘Most recognized’ are IPC and JEDEC standards.

But even within IPC there are multiple versions. IPC-7351B is the most recent from IPC (at the time of writing).

I learned* there is no such thing as a “standard” 0603 (1608 metric) package outline for example. Instead, a 0603 footprint (aka ‘land pattern’) depends on desired board density and the used soldering technique in manufacturing (wave or reflow).

*by reading in the standards itself as well as these interesting threads:
here,
here
and
here.

This was quite a revelation to me as I previously assumed those generic packages were standardized in a way (because they are so common).

Anyway, I accepted this reality of chaotic standards and I understand I had to choose one standard for myself to work with.
I choose IPC as it is by far the most used in the industry.

My CAD software (Autodesk Eagle) offers a very practical package generator which satisfies IPC norms. It generates a land pattern for - and 3D model of - a desired package which is IPC compliant.

However now I'm faced with a dilemma. I discovered not only a “standard 0603” does not exist (which I'll solve by sticking to one standard), but apparently even a “standard LQFP48”, for example, does not exist!

For example: take following components
from Microchip
, from TI
, from STM
; they all have an LQFP48 package with same case size and pad pitch.

However, all three datasheets specify a slightly different land pattern for what I thought was the exact same LQFP48. The difference is subtle, and only affects the extension (length) of the pad and pad width (0,25 - 0,27 - 0,30 respectively), but it is there!

So what is the rule of thumb now? What would experienced PCB designers choose if these components were in the same design?

option 1: Using 3x a different land pattern for what is actually described as the same package outline.

option 2: Use the IPC-7351 compliant LQFP48* for all three.

*in IPC terms this would be: QFP50P900X900X160-48

Since the differences are so subtle, I know both options would probably turn out just fine but what is the general rule here?
What is ‘good practice’?

Many thanks!

In my experience, you can safely stick to the IPC standards, which by the way also suggest three different footprints for each part: Least, Most, and Nominal. It is up to you which one to select, depending mostly on the manufacturing process. In most cases you will use the Nominal pad sizes.

In general terms, the footprint that is suggested by the manufacturers on the datasheet, is simply what they have used to design the evaluation kits, and worked well for the process they used; I can tell you this, because I used to work for one of the big semiconductor companies, and this is what happened. The footprints were usually derived from the IPC standards, which should always be your reference, unless it is a completely non standard part.

When it comes to mass production you will go through enough PCB revisions to optimise the footprint, and at that point the PCB manufacturer/assembly house will take over and modify the land patterns to match their manufacturing process, and ensure good yield.

The correct footprint to use for a component land is 'one that works'.

This isn't so flip as it sounds.

What does a land pattern have to do in order to 'work'?

a) it must connect each component leg to its pad

b) it must not connect it to adjacent pads

c) it must pull the component into correct alignment when the solder is liquid

d) it must be visually inspectable

These taken together mean the lands must be at least as big as the lead, but not too close together. There is considerable latitude in how much bigger the lands can be. It's this wide latitude that allows there to be multiple designs.

A land that is much bigger will satisfy (a) and (d), but might get solder stuck between the lands so fall foul of (b).

Whether a particular footprint is solderable without getting connectivity between lands depends to a large extent on the process the board assembler uses, and to some extent on the thermal capacity and lead positioning accuracy of the component. If different manufacturers use different assembler processes to refine the footprint, it's not surprising that they might end up with slightly different pad sizes.

What is surprising is that the process works as well and as often as it does.

A case in point. I was once using a 0402 packaged diode, and the manufacturer was aiming it towards very small, so very high packing density, boards. As a result, they specified a land pattern that had copper areas exactly the same size as the component pads. This resulted in a small solder volume with no side or toe fillets, that our particular in-house reflow process often failed to assemble properly. I had to fight our reactionary production manager and his 'always use the manufacturers recommendation' footprint policy to use lands that were larger and more suited to our solder process. Once we had more solder, and fillets, the yield went back to 100%. It's likely that were we using a thicker solderpaste stencil it would have soldered OK, but that would have been inappropriate for our other components with their more generous lands.